1. Field of the Invention
The present invention relates to a data reading technique of a semiconductor storage apparatus, particularly to a fast data reading technique.
2. Description of the Related Art
When a semiconductor storage apparatus (e.g., NOR type flash memory) is accessed at random, a series of reading operation including: selecting a cell for each address input; sensing cell data; and outputting the data is repeated. Therefore, a certain given time is required, and the data cannot be outputted faster.
On the other hand, a serial access operation includes: selecting cells corresponding to a plurality of addresses present on the same word line at the same time; sensing the data; latching the sensed data; and sequential outputting the latched data in synchronization with a clock from the outside. Therefore, a fast data reading is apparently realized.
Furthermore, when the latched data is sequential outputted, a next group of cells are sensed in a chip. Since a so-called xe2x80x9cpipeline readingxe2x80x9d is performed, an internal reading delay can be eliminated in and after a first access, and the fast data reading is enabled.
The xe2x80x9cpipeline readingxe2x80x9d has heretofore been realized by dividing a memory cell array into two, and disposing a decoder and sense amplifier in the two arrays, respectively. Therefore, a chip area has largely increased.
A semiconductor device according to an aspect of the invention comprises: first, second, third, fourth bit lines and a redundant bit line; a first sense amplifier coupled to the first and second bit lines; a second sense amplifier coupled to the third and fourth bit lines; a redundant sense amplifier coupled to the redundant bit line; a first column gate transistor having a current path coupled to the first bit line; a second column gate transistor having a current path coupled to the second bit line; a third column gate transistor having a current path coupled to the third bit line, a fourth column gate transistor having a current path coupled to the fourth bit line; a redundant column gate transistor having a current path coupled to the redundant bit line; a first column select line coupled to a gate of the first column gate transistor; a second column select line coupled to a gate of the second column gate transistor and passing through the first bit line; a third column select line coupled to a gate of the third column gate transistor and passing through the first and second bit lines, a fourth column select line coupled to a gate of the fourth column gate transistor and passing through the first; second and third bit lines; and a redundant column select line coupled to a gate of the redundant column gate transistor and passing through the first, second, third and fourth bit lines.